论文

2027

1. HPCA’27

   

   GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow

   Zirui Ma, Zhihua Fan, Haibin Wu, Dongrui Fan, Xiaochun Ye, and Wenming Li

   In 33rd IEEE International Symposium on High-Performance Computer Architecture, 2027

   CCF-A · Accepted

   Abs arXiv Bib Web

   4D Gaussian Splatting (4DGS) enables high-quality real-time novel-view synthesis for dynamic scenes, supporting free-viewpoint video, mobile XR, and autonomous systems at the edge. Methods using explicit 4D distributions, keyframe interpolation, or anchor binding share two GPU data-movement bottlenecks. Temporal filtering follows model record loading, wasting LPDDR5 bandwidth on inactive data. Frame-isolated execution also overlooks highly overlapping active sets and depth relationships across adjacent frames, reloading shared attributes when working sets exceed on-chip cache capacity. To address these bottlenecks, we present GSPIM, a temporal-locality-aware 4DGS accelerator for PIM-enabled edge devices. Polymorphic PIM adapts a shared near-memory datapath to representation-specific field layouts and selection procedures. It filters and compacts valid data into contiguous inputs before the GPU accesses complete attributes, reducing ineffective transfers. Multi-Frame Rendering Dataflow reuses active attributes and stable depth relationships within a temporal window, reducing repeated work across frames. Hybrid Dataflow Scheduling overlaps near-memory data preparation with GPU rendering to reduce waiting. Evaluation combines a GPU-PIM model calibrated to Jetson AGX Orin 64 GB with a 1z DRAM physical implementation of the added circuits. Across three 4DGS methods and six dynamic scenes, GSPIM achieves a 4.15x geometric-mean speedup and a 4.99x geometric-mean energy-efficiency improvement over a fully optimized frame-by-frame GPU baseline. The maximum scene-level PSNR difference is 0.011 dB, and the added physical footprint is 18.7172 square millimeters across 32 LPDDR5 dies.

   @inproceedings{ma2027gspim,
     title = {GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow},
     author = {Ma, Zirui and Fan, Zhihua and Wu, Haibin and Fan, Dongrui and Ye, Xiaochun and Li, Wenming},
     booktitle = {33rd IEEE International Symposium on High-Performance Computer Architecture},
     year = {2027},
   }

2. HPCA’27

   

   HARP: A Hierarchical Attention and Representation Sparsity Accelerator for Diffusion Transformers

   Yudong Mu, Minnan Pei, Zhihua Fan, Zirui Ma, Gang Li, Zhuoran Song, Yu Huang, Dongrui Fan, Xiaochun Ye, and Wenming Li

   In 33rd IEEE International Symposium on High-Performance Computer Architecture, 2027

   CCF-A · Accepted

   Abs Bib Web

   Diffusion Transformers (DiTs) enable high-quality image and video generation, but their iterative denoising repeatedly executes a full Transformer over long token sequences, making inference prohibitively expensive. Existing accelerators exploit spatial or temporal redundancy to select which tokens, interactions, or operators execute, or reduce arithmetic through quantization; the BF16 activations that remain are still largely processed as dense arithmetic objects. Organizing DiT execution around spatially local Token Regions exposes a complementary hierarchy: Inter-Region Attention Sparsity across Region Pairs and Intra-Region Representation Sparsity within Region Slices. Exploiting either level directly is difficult because low-mass attention interactions collectively preserve long-range information, while the quality impact of collapsing numeric planes depends on the denoising trajectory. We present HARP, an algorithm–hardware co-design that addresses these constraints with residual-compensated windowing and trajectory-aware PlaneClear. The former recomputes only mass-selected Region Pairs and reuses a window-matched residual to restore omitted output information; the latter clears low-impact BF16 components to collapse complete numeric planes across attention, projections, and FFNs. A region-centric, bit-interleaved accelerator coordinates selected-region delivery and persistent residual state globally while balancing irregular plane workloads locally. Across six image and video DiTs, HARP achieves a 12.24x geometric-mean speedup over NVIDIA H100 and 3.21x over DSTAR, with at most 2.32% degradation in the primary quality metric and modest area overhead over BitRed.

   @inproceedings{mu2027harp,
     title = {HARP: A Hierarchical Attention and Representation Sparsity Accelerator for Diffusion Transformers},
     author = {Mu, Yudong and Pei, Minnan and Fan, Zhihua and Ma, Zirui and Li, Gang and Song, Zhuoran and Huang, Yu and Fan, Dongrui and Ye, Xiaochun and Li, Wenming},
     booktitle = {33rd IEEE International Symposium on High-Performance Computer Architecture},
     year = {2027},
   }

2026

1. MICRO’26

   

   SCARF: A Scene-Adaptive Depth-Guided G-3DGS Encoder Accelerator with Semantic Reuse and Fused Dataflow

   Zirui Ma, Zhihua Fan, Haibin Wu, Wenxing Li, Fulin Zhang, Dongrui Fan, Xiaochun Ye, and Wenming Li

   In 59th IEEE/ACM International Symposium on Microarchitecture, 2026

   CCF-A · Accepted (31st ChinaSys Oral)

   ALL AE Badges Abs arXiv Bib Page Supp Code Web

   Awarded all three MICRO 2026 Artifact Evaluation badges: Artifacts Available, Artifacts Evaluated - Functional, and Results Reproduced. Artifact Evaluation · Evaluated Artifact

   Depth-guided, cost-volume-based Generalizable 3D Gaussian Splatting (G-3DGS) encoders reconstruct scenes as sets of Gaussian primitives directly from multi-view images without requiring per-scene optimization, thereby facilitating feed-forward novel-view synthesis on edge computing platforms. However, their shared encoder architecture presents two primary bottlenecks. First, the per-pixel depth search disregards semantic similarity within the 2D feature space, causing depth search operations to account for over 65% of memory traffic due to redundant exhaustive candidate scans. Second, the sequential pipeline of depth prediction followed by Gaussian generation neglects local 3D geometric continuity, resulting in more than 52% of generated Gaussians being redundant prior to instantiation. In this paper, we introduce SCARF, a dataflow-co-designed accelerator that aligns each bottleneck with a corresponding scene-level regularity. To mitigate the first bottleneck, Feature Similarity Depth Reuse reconceptualizes depth search as a problem of semantic locality: depth consistency is determined by affinity in feature space rather than physical address proximity. It transforms exhaustive per-pixel depth searches into anchor-centered local searches. To overcome the second bottleneck, Scene-Adaptive Early Sparsification disrupts the conventional serial depth-to-materialization boundary by probing each tile to infer local scene regularity. It then selectively activates only the minimally sufficient generation pathway, eliminating redundant Gaussian computations before primitive instantiation. On a 27.8 square millimeter 28 nm post-layout design, SCARF delivers a 2.94x geometric-mean end-to-end speedup with maximum PSNR degradation below 0.072%, 2.23 inferences per joule, and 34.5x GPU energy efficiency.

   @inproceedings{ma2026scarf,
     title = {SCARF: A Scene-Adaptive Depth-Guided G-3DGS Encoder Accelerator with Semantic Reuse and Fused Dataflow},
     author = {Ma, Zirui and Fan, Zhihua and Wu, Haibin and Li, Wenxing and Zhang, Fulin and Fan, Dongrui and Ye, Xiaochun and Li, Wenming},
     booktitle = {59th IEEE/ACM International Symposium on Microarchitecture},
     year = {2026},
   }

2. DAC’26

   

   AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices

   Zirui Ma, Zhihua Fan, Wenxing Li, Haibin Wu, Fulin Zhang, Wenming Li, and Xiaochun Ye

   In Proceedings of the 63rd ACM/IEEE Design Automation Conference, Jul 2026

   CCF-A · Published

   Abs DOI arXiv Bib Code Web

   Speculative decoding enhances the inference efficiency of large language models (LLMs) by generating drafts using a small draft language model (DLM) and verifying them in batches with a large target language model (TLM). However, adaptive drafting inference on a mobile single-NPU-PIM system faces idle overhead in traditional operator-level synchronous execution and wasted computation in asynchronous execution due to fluctuations in draft length. This paper introduces AHASD, a task-level asynchronous mobile NPU-PIM heterogeneous architecture for speculative decoding. Notably, AHASD achieves parallel drafting on the PIM and verification on a single NPU through task-level DLM-TLM decoupling and specifically, it incorporates Entropy-History-Aware Drafting Control and Time-Aware Pre-Verification Control to dynamically manage adaptive drafting algorithm execution and pre-verification timing, suppressing invalid drafting based on low-confidence drafts. Additionally, AHASD integrates Attention Algorithm Units and Gated Task Scheduling Units within LPDDR5-PIM to enable attention link localization and sub-microsecond task switching on the PIM side. Experimental results for different LLMs and adaptive drafting algorithms show that AHASD achieves up to 4.2x in throughput and 5.6x in energy efficiency improvements over a GPU-only baseline, and 1.5x in throughput and 1.24x in energy efficiency gains over the state-of-the-art GPU+PIM baseline, with hardware overhead below 3% of the DRAM area.

   @inproceedings{ma2026ahasd,
     title = {AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices},
     author = {Ma, Zirui and Fan, Zhihua and Li, Wenxing and Wu, Haibin and Zhang, Fulin and Li, Wenming and Ye, Xiaochun},
     booktitle = {Proceedings of the 63rd ACM/IEEE Design Automation Conference},
     series = {DAC '26},
     pages = {1--7},
     month = jul,
     year = {2026},
     publisher = {ACM},
     doi = {10.1145/3770743.3803965},
   }

3. ISCA’26

   

   MLX: Multi-Layer Execution for Structured LLM Workload Acceleration on Spatial Architectures

   Haibin Wu, Wenming Li, Zhihua Fan, Zirui Ma, Yuqun Liu, Tengfei Xia, Yanhuan Liu, Kunming Zhang, Xiaochun Ye, Dongrui Fan, and Jian Weng

   In 53rd IEEE/ACM International Symposium on Computer Architecture, Jun 2026

   CCF-A · Published

   Best Paper Nomination Abs DOI Bib Web

   Nominated for the ISCA 2026 Best Paper Award.

   Structured sparsity is a promising approach to scaling large-language-model (LLM) inference, but existing forms such as block-diagonal matrices, FFT mixing, and butterfly factorization map inefficiently to GPUs due to deep stage dependencies and limited bulk parallelism. This paper presents MLX, an algorithm-architecture co-design that proposes a unified structured-sparse transformer framework combining semantic-aware FFT, hierarchical butterfly sparsity, and structured attention, and maps it efficiently onto spatial dataflow architectures. MLX is built on Closed Dependency Components (CDCs), a formal abstraction for deterministic forward-only dataflow regions that can be folded across layers and pipelined on compact meshes. Based on this abstraction, MLX introduces a multi-layer execution model with bounded-hop skip-hop routing, tag-based scheduling, and decoupled compute/transfer pipelines to overlap communication and computation across deep operators. We prototype MLX in 12 nm and show that it achieves 3.2x speedup and 3.0x energy savings over Jetson Xavier. A transformer-specialized reduced design further delivers up to 5.7x speedup over prior sparse accelerators. MLX also scales nearly linearly to 8x8 meshes and remains effective for long sequences from 1K to 4K, demonstrating that structured operator semantics can be translated into efficient spatial execution for sparse LLMs.

   @inproceedings{wu2026mlx,
     title = {MLX: Multi-Layer Execution for Structured LLM Workload Acceleration on Spatial Architectures},
     author = {Wu, Haibin and Li, Wenming and Fan, Zhihua and Ma, Zirui and Liu, Yuqun and Xia, Tengfei and Liu, Yanhuan and Zhang, Kunming and Ye, Xiaochun and Fan, Dongrui and Weng, Jian},
     booktitle = {53rd IEEE/ACM International Symposium on Computer Architecture},
     pages = {1--16},
     month = jun,
     year = {2026},
     doi = {10.1109/ISCA66397.2026.00017},
   }

4. JCST’26

   

   HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding

   Bing Wang, Zirui Ma, Hai-Bin Wu, Fu-Lin Zhang, Yue Wang, Zhi-Hua Fan, Wen-Ming Li, Xiao-Chun Ye, and Dong-Rui Fan

   Journal of Computer Science and Technology, Mar 2026

   CCF-B · Published

   Abs DOI Bib Page PDF

   Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common general-purpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design.

   @article{wang2026harld,
     title = {HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding},
     author = {Wang, Bing and Ma, Zirui and Wu, Hai-Bin and Zhang, Fu-Lin and Wang, Yue and Fan, Zhi-Hua and Li, Wen-Ming and Ye, Xiao-Chun and Fan, Dong-Rui},
     journal = {Journal of Computer Science and Technology},
     volume = {41},
     number = {2},
     pages = {774--790},
     month = mar,
     year = {2026},
     doi = {10.1007/s11390-025-5052-5},
   }

5. FCS’26

   

   DFU-L: A Latency-Sensitive Dataflow Architecture with NoC and Streaming Optimizations for Edge DSP

   Haibin Wu, Zhihua Fan, Zhen Wang, Zirui Ma, Wenxing Li, Haoran Tong, Tengfei Xia, Xiaochun Ye, and Wenming Li

   Frontiers of Computer Science, 2026

   CCF-B · Accepted

   Abs DOI Bib Page

   Dataflow architectures are attractive for real-time edge workloads because structured computation and streaming data movement expose abundant instruction-level and pipeline parallelism. However, as working sets shrink and iteration latency becomes critical, conventional spatial dataflow fabrics can become limited by on-chip transfer and control overheads rather than raw compute throughput. Fine-grained inter-PE dependences, scratchpad-bank contention, and frequent instruction or kernel switching introduce non-negligible stalls, reducing effective PE utilization. This paper presents DFU-L, a latency-sensitive coarse-grained dataflow architecture that improves latency overlap across on-chip communication, streaming memory access, and execution switching. DFU-L first introduces a forwarding-oriented NoC with dataflow-unblocking arbitration to accelerate inter-PE operand delivery and reduce dependence-transfer latency. It then organizes memory accesses into clustered fetch domains and uses a paced streaming fetch engine to smooth scratchpad-bank service under memory-bound thin-DFG execution. Finally, DFU-L reuses idle forwarding windows to overlap instruction and kernel switching with the tail of the current dataflow execution, reducing control-transition overhead. We evaluate DFU-L with a cycle-accurate simulator calibrated against RTL and a 12 nm, 1 GHz implementation. Across representative edge DSP kernels, DFU-L achieves up to 1.92x speedup and 1.45x on average over a mesh baseline. It improves energy efficiency by 1.14x–2.06x over Plasticine, reduces energy-delay product by up to 2.18x compared with state-of-the-art DSP accelerators, and delivers 1.24x normalized energy efficiency over high-performance dataflow designs.

   @article{wu2026dful,
     title = {DFU-L: A Latency-Sensitive Dataflow Architecture with NoC and Streaming Optimizations for Edge DSP},
     author = {Wu, Haibin and Fan, Zhihua and Wang, Zhen and Ma, Zirui and Li, Wenxing and Tong, Haoran and Xia, Tengfei and Ye, Xiaochun and Li, Wenming},
     journal = {Frontiers of Computer Science},
     year = {2026},
     doi = {10.1007/s11704-026-61054-2},
   }

6. CAL’26

   

   BISC: Rethinking Instruction Set Abstractions at Block Granularity

   An Zhong, Hanzhi Hu, Zirui Ma, Mengzhu Li, Haibin Wu, Fulin Zhang, Jinyi Deng, Ceyu Xu, Wenming Li, Yang Hu, and Jian Weng

   IEEE Computer Architecture Letters, May 2026

   Published

   Abs DOI Bib Page

   Most widely deployed ISAs for general-purpose processors expose a centralized register file and instruction-granular control flow, forcing modern CPUs to rely on complex microarchitectural mechanisms to reconcile execution with architectural state. Even in simple in-order designs, these abstractions impose back-and-forth execution overheads, while more aggressive processors further amplify them through register renaming, speculation, and in-order retirement. This letter presents the Block-based Instruction Set Computer (BISC), which rethinks ISA abstractions at block granularity. BISC eliminates architectural destination registers by binding each instruction’s result to its position within a block, enabling block-local execution driven by operand availability while preserving control-flow semantics across blocks. Control flow is resolved at block entry, amortizing fetch and control overhead across multiple operations and enabling efficient expression of conditional selection without additional control-flow edges. We evaluate BISC using a single-issue in-order core with comparable area to a RISC-V baseline. Despite executing more operations and incurring a larger code footprint, BISC achieves a 34% geometric mean speedup across benchmarks. These results demonstrate that ISA-level execution abstractions play a critical role in processor efficiency, independent of microarchitectural optimizations.

   @article{zhong2026bisc,
     title = {BISC: Rethinking Instruction Set Abstractions at Block Granularity},
     author = {Zhong, An and Hu, Hanzhi and Ma, Zirui and Li, Mengzhu and Wu, Haibin and Zhang, Fulin and Deng, Jinyi and Xu, Ceyu and Li, Wenming and Hu, Yang and Weng, Jian},
     journal = {IEEE Computer Architecture Letters},
     volume = {25},
     number = {1},
     pages = {222--225},
     month = may,
     year = {2026},
     doi = {10.1109/LCA.2026.3690895},
   }